Microelectronic devices are often manufactured in and on silicon wafers and on other types other substrates. Such integrated circuits may include millions of transistors, such as metal oxide semiconductor (MOS) field effect transistors, as are well known in the art. In the fabrication of MOS transistors, it is common to form doped junctions by ion implantation. For example, using a gate structure as a mask, an ion implantation may form implanted regions, such as source/drain regions, as are known in the art. As a result of the ion implantation of a dopant species, damage may occur to a semiconductor substrate. In addition, many of the implanted species may not find substitutional sites i.e., they may remain unactivated within the crystal lattice of the substrate.
In order to repair the damage and to activate the species into substitutional sites, it is common to use an annealing or heating step. For example, rapid thermal annealing (RTA) and diffusion furnace annealing are two conventional processes that may be utilized to anneal semiconductor devices.
While conventional annealing techniques may commonly be used when a gate structure comprises a polysilicon material, problems may occur when the gate structure comprises a metal material. For example, one problem that may occur is that a metal gate material may undergo undesired phase changes when using a conventional annealing process. Such phase changes may change the work function of a metal gate structure, which may adversely affect the performance of a transistor.
Another problem that may occur when using conventional annealing techniques with a metal gate structure is that the metal gate material may diffuse into an underlying gate dielectric layer, for example. Referring to FIG. 2a, a gate structure 202 may comprise a gate dielectric layer 204, a metal layer 206 (such as a work function metal layer, as is known in the art), a polysilicon fill layer 208, and a spacer 210.
The gate structure 202 may also comprise source/drain regions 212 that are implanted with a plurality of implanted species 216. The polysilicon fill layer 208 may also be implanted with the plurality of implanted species 216. A pre-anneal depth 220 of the metal layer 206 may be bounded by the top 205 of the underlying gate dielectric layer 204 and the bottom 207 of the polysilicon fill layer 208. The gate structure 202 may be disposed on a substrate 203, such as a silicon substrate. A conventional annealing process 218, such as an RTA or diffusion process, may be performed on the gate structure 202.
After the conventional annealing process 218 has been performed, the plurality of implanted species 216 may be activated within the crystal lattice of the gate structure 202, such as within the source/drain regions 212. Unfortunately, the conventional annealing process may be of such a time duration that the metal layer 206 may undergo a phase change, or may diffuse into the underlying gate dielectric layer 204 and/or may diffuse into the upper polysilicon fill layer 208 (see FIG. 2b). Consequently, a post-anneal depth 226 of the metal layer 206 may be larger than the pre-anneal depth 220 of the metal layer 206. This is due to the diffused polysilicon fill layer portion 222 of the metal layer 206 and the diffused gate dielectric layer portion 224 of the metal layer 206.
The phase change or the diffusion of the metal layer 206 into the gate dielectric layer 204 and/or into the upper polysilicon fill layer 208 may cause undesirable changes in the work function of the metal layer 206, as well as shorting etc. that may adversely affect the performance of the device. In addition, a source/drain junction depth 228 may be larger than is desired for a particular application, due to the amount of time required to anneal the gate structure 202 using the conventional annealing process 218.
For example, the ratio of the source/drain junction depth 228 to a source/drain junction length 230 may be greater than about 1:2, which may be undesirable for a particular application since shallower source/drain regions 212 typically result in faster device performance, as is known in the art. Thus, there is a need for better methods of annealing implanted regions in the manufacture of integrated circuits that comprise metal gates. The methods and structures of the present invention provide such methods.